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LT1768 High Power CCFL Controller for Wide Dimming Range and Maximum Lamp Lifetime DESCRIPTIO
The LT(R)1768 is designed to control single or multiple cold cathode fluorescent lamp (CCFL) displays. A unique Multimode Dimming scheme* combines both linear and PWM control functions to maximize lamp life, efficiency, and dimming range. Accurate maximum and minimum lamp currents can be easily set. The LT1768 can detect and protect against lamp failures and overvoltage start-up conditions. It is designed to provide maximum flexibility with a minimum number of external components. The LT1768 is a current mode PWM controller with a 1.5A MOSFET driver for high power applications. It contains a 350kHz oscillator, 5V reference, and a current sense comparator with a 100mV threshold. It operates from an 8V to 24V input voltage. The LT1768 also has undervoltage lockout, thermal limit, and a shutdown pin that reduces supply current to 65A. It is available in a small 16-lead SSOP package.
, LTC and LT are registered trademarks of Linear Technology Corporation. Multimode Dimming is a trademark of Linear Technology Corporation. *Patent Pending
FEATURES
s s s
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Ultrawide Multimode DimmingTM Range Multiple Lamp Capability Programmable PWM Dimming Range and Frequency Precision Maximum and Minimum Lamp Currents Maximize Lamp Lifetime No Lamp Flicker Under All Supply and Load Conditions Open Lamp Detection and Protection 350kHz Switching Frequency 1.5A MOSFET Gate Driver 100mV Current Sense Threshold 5V Reference Voltage Output The 16-Lead SSOP Package
APPLICATIO S
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Desktop Flat Panel Displays Multiple Lamp Displays Notebook LCD Displays Point of Sale Terminal Displays
TYPICAL APPLICATIO
C4-WIMA MKP2 L1-COILTRONICS UP4-680 T1-2 CTX110607 IN PARALLEL Q1-ZDT1048 *R5 CAN BE METAL PCB TRACE
33pF LAMP 6 LAMP VIN 8V - 24V C1 33F PGND DI02 DI01 GATE VIN VREF 5V 0.1F 33pF 4 T1 10
5
3
2 C4 0.33F
1
250 1/4W Q1 Q1
C2 0.033F
SENSE FAULT LT1768 VC SHDN AGND CT PROG C4 10F RMIN RMAX PWM R4 16.2k
MBRS130T3 R2 40.2k
L1 68H
C3 0.1F PROG 0V TO 5V OR 1kHz PWM
Si3456DY 100 R3 60.4k
R1 49.9k
2200pF
R5* 0.025
1768 TA01
Figure 1. 14W CCFL Supply Produces a 100:1 Dimming Ratio While Maintaining Minimum and Maximum Lamp Current Specifications
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Lamp Output and Dimming Ratio vs Lamp Current
10000
1000 DIMMING RATIO (NITS/NITS) 100 LAMP OUTPUT (NITS) 10
1 LAMP MANUFACTURERS SPECIFIED CURRENT RANGE 0.1 0 2 6 8 4 LAMP CURRENT (mA) 10
1768 TA01b
1
LT1768
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW PGND DI01 DI02 SENSE VC AGND CT PROG 1 2 3 4 5 6 7 8 16 GATE 15 VIN 14 VREF 13 FAULT 12 SHDN 11 RMIN 10 RMAX 9 PWM
Input Voltage (VIN Pin) ............................................ 28V SHDN Pin Voltage .................................................... 28V FAULT Pin Voltage ................................................... 28V PROG Pin Voltage ................................................... 5.5V PWM Pin Voltage .................................................... 4.5V CT Pin Voltage ........................................................ 4.5V SENSE Pin Voltage .................................................... 1V DIO1, DIO2 Input Current ................................... 50mA RMAX Pin Source Current ..................................... 750A RMIN Pin Source Current ..................................... 750A VREF Pin Source Current ....................................... 10mA Operating Junction Temperature Range LT1768C ................................................ 0C to 125C LT1768I ............................................ - 40C to 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering 10 sec)................... 300C
ORDER PART NUMBER LT1768CGN LT1768IGN GN PART MARKING 1768 1768I
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 100C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VVIN = 12V, IDIO1/2 = 250A, VPROG = 0V, VPWM = 2.5V, IRMAX = -100A, IRMIN = -100A, unless otherwise specified.
SYMBOL IQ ISHDN PARAMETER Supply Current Supply Current in Shutdown SHDN Pin Pull-Up Current SHDN Threshold Voltage SHDN Threshold Hysteresis VIN Undervoltage Lockout VIN Undervoltage Lockout VREF REF Voltage REF Line Regulation REF Load Regulation VRMAX VRMIN FSW RMAX Pin Voltage RMIN Pin Voltage Switching Frequency Maximum Duty Cycle Minimum ON Time IPROG VPROG PROG Pin Input Bias Current PROG Pin Voltage for Zero Lamp Current PROG Pin Voltage for Minimum Lamp Current PROG Pin Voltage for Maximum Lamp Current VPROG = 0.75V, VSENSE = 0V VPROG = 0.75V, VSENSE = 0V VPROG = 0.75V, VSENSE = 150mV VPROG = 5V (Note 2) (Note 3) (Note 4)
q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS 9V< VVIN < 24V VSHDN = 0V VSHDN = 0V VSHDN Off to On VIN Off to On VIN On to Off IREF = -1mA VVIN 8V to 24V IREF = -1mA IREF -1mA to -10mA
q q q q q q q q q q q q q
MIN
TYP 7 65
MAX 8 100 12 1.8 300 8.2 7.6 5.1 20 20 1.275 1.30 410
UNITS mA A A V mV V V V mV mV V V kHz % ns
4 0.6 100 7.2 7.1 4.9
7 1.26 200 7.9 7.4 5 7 10
1.225 1.22 300
1.25 1.26 350 93 125 100
500 0.55 1.1 4.2
0.45 0.9 3.8
0.5 1 4
2
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nA V V V
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LT1768
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, VVIN = 12V, IDIO1/2 = 250A, VPROG = 0V, VPWM = 2.5V, IRMAX = -100A, IRMIN = -100A, unless otherwise specified.
SYMBOL IPWM PARAMETER PWM Input Bias Current PWM Duty Cycle PWM Frequency VDIO1/2 VVCCLAMP ISENSE VSENSE DIO1/2 Positive Voltage DIO1/2 Negative Voltage VC High Clamp Voltage VC Switching Threshold SENSE Input Bias Current SENSE Threshold for Current Limit IDIO1/2 to IRMAX Ratio VPROG = 1.75 CT = 0.22F (Note 7) IDIO = 14mA IDIO = -14mA VPROG = 4.5V (Note 8) VPROG = 4.5V (Note 8) VSENSE = 0V VVC = VVCCLAMP, Duty Cycle < 50%, VPROG = 1V VVC = VVCCLAMP, Duty Cycle 80%, VPROG = 1V VPROG = 4.5V (Note 5) VPROG = 4.5V, IDIO1 or IDIO2 = 0, VVC = 2.5V, (Note 5) IDIO1/2 to IRMIN Ratio VPROG < 0.75V (Note 6) VPROG < 0.75V, IDIO1 or IDIO2 = 0, VVC = 2.5V, (Note 6) IGATE GATE Drive Peak Source Current GATE Drive Peak Sink Current GATE Drive Saturation Voltage GATE Drive Clamp Voltage GATE Drive Low Saturation Voltage Open LAMP Threshold FAULT Pin Saturation Voltage FAULT Pin Leakage Current Thermal ShutdownTemperature Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: This is the threshold voltage where the lamp current switches from zero current to minimum lamp current. For VPROG less than the threshold voltage, lamp current will be at zero. For VPROG greater than the threshold voltage, lamp current will be equal to the minimum lamp current. Minimum lamp current is set by the value of the resistor from the RMIN pin to ground. See Applications Information for more details. Note 3: This is the threshold voltage where the device starts to pulse width modulate the lamp current. For VPROG less than the threshold voltage, lamp current will be equal to the minimum lamp current. For VPROG greater than the threshold voltage, lamp current will be pulse width modulated between the minimum lamp current and some higher value. Minimum lamp current is set by the value of the resistor from the RMIN pin to ground. The higher value lamp current is a function of the RMAX resistor to ground value, and the voltages on the PWM and PROG pins. See Applications Information for more details. Note 4: This is the threshold voltage where the lamp current reaches its maximum value. For VPROG greater than the threshold voltage, there will be no increase in lamp current. For VPROG less than the threshold voltage, lamp current will be at some lower value. Maximum lamp current is set by VVIN = 12V, IGATE = -100mA, VPROG = 4.5V VVIN = 24V, IGATE = -10mA, VPROG = 4.5V IGATE = 100mA (Note 9) IFAULT = 1mA, IDI01, IDI02 = 0A, VPROG = 4.5V VFAULT = 5V
q q q q q
ELECTRICAL CHARACTERISTICS
CONDITIONS
q
MIN 45 90
TYP 0.6 50 110 1.7 -1.1
MAX 4 55 130 1.9 -1.3 3.9 0.95 -30 115 104 55 11 11
UNITS A % Hz V V V V A mV mV A/A A/A A/A A/A A A V
3.6 0.5 85 94 45 9 9
3.7 0.7 -25 100 90 98 49 10 10 1.5 1.5
9.8
10.2 12.5 0.4 14 0.6 150 0.3 100
V V A V nA C
100
125 0.2 20 160
the value of the resistor from the RMAX pin to ground. The lower value lamp current is a function of the RMIN and RMAX resistors, and the voltages on the PWM and PROG pins. See Applications Information for more details. Note 5: IDIO1/2 to IRMAX ratio is determined by setting IRMAX to -100A, VPROG to 4.5V, VVC to 2.5V, and then ramping a DC current out of the DIO1/2 pins from zero until the DC current in the VC voltage source current equals zero. The IDIO1/2 to IRMAX ratio is then defined as (IDIO1 + IDIO2)/IRMAX. See Applications Information for more details. Note 6: IDIO1/2 to IRMIN ratio is determined by setting IRMIN to -100A, VPROG to 0.75V, VVC to 2.5V, and then ramping a DC current out of the DIO1/2 pins from zero until the DC current in the VC voltage source current equals zero. The IDIO1/2 to IRMIN ratio is then defined as (IDIO1 + IDIO2)/IRMIN. See Applications Information for more details. Note 7: The PWM frequency is set by the equation PWMFREQ = 22Hz/ CT(F). Note 8: For VC voltages less than the switching threshold, GATE switching is disabled. Note 9: An open lamp will be detected if either IDIO1 or IDIO2 is less than the threshold current for at least 1 full PWM cycle.
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LT1768 TYPICAL PERFOR A CE CHARACTERISTICS
VREF vs Temperature
5.10 5.08 5.06 IREF = -1mA 1.30
SHUTDOWN CURRENT (A)
VREF VOLTAGE (V)
5.04
VOLTAGE (V)
5.02 5.00 4.98 4.96 4.94 4.92 4.90 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125
Supply Current vs Input Voltage
10
7.40 7.30
SUPPLY CURRENT (mA)
7.20
7.10 7.00 6.90 6.80 6.70 6.60 6.50
6
SHUTDOWN CURRENT (A)
8
SUPPLY CURRENT (mA)
4
2
0 0 5
15 INPUT VOLTAGE (V)
10
SHDN Pull-Up Current vs Input Voltage
10
SHDN PULL-UP CURRENT (A)
VSHDN = 0V
SHUTDOWN VOLTAGE (V)
8
UNDERVOLTAGE LOCKOUT (V)
6
4
2
0 0 5 15 10 INPUT VOLTAGE (V) 20 25
1768 G07
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UW
1768 G01
VRMIN, VRMAX vs Temperature
IRMIN = -100A 1.29 IRMAX = -100A 1.28 1.27 1.26 1.25 1.24 1.23 1.22 1.21 1.20 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125 VRMIN(V) VRMAX(V)
Supply Current in Shutdown vs Temperature
80 76 72 68 64 60 56 52 48 44 40 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125 VSHDN = 0V
1768 G02
1768 G03
Supply Current vs Temperature
100
Supply Current in Shutdown vs Input Voltage
VSHDN = 0V
80
60
40
20
20
25
1768 G04
6.40 -50
0
-25 0 75 TEMPERATURE (C) 25 50 100 125
0
5
10 15 INPUT VOLTAGE (V)
20
25
1768 G06
1768 G05
Shutdown Threshold Voltage vs Temperature
2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0 -50
Undervoltage Lockout Threshold vs Temperature
8.20 8.10
VSHDN OFF TO ON
8.00 7.90 7.80 7.70 7.60 7.50 7.40 7.30
VUVL OFF TO ON
VSHDN ON TO OFF
VUVL ON TO OFF
-25
50 0 25 75 TEMPERATURE (C)
100
125
7.20 -50
-25
50 0 25 75 TEMPERATURE (C)
100
125
1768 G08
1768 G09
LT1768 TYPICAL PERFOR A CE CHARACTERISTICS
Switching Frequency vs Temperature
400 390
SWITCHING FREQUENCY (kHz)
380
PWM FREQUENCY (Hz)
360 350 340 330 320 310 300 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125
108 104 100 96 92 88 84 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125
FAULT VOLTAGE (V)
370
FAULT Pin Saturation Voltage vs Current
450 400 IDIO1 = 0A IDIO2 = 0A
350 300 250 200 150 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 IFAULT (mA)
1768 G13
35 30 25 20 15 10 5 0 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125
GATE CLAMP VOLTAGE (V)
FAULT VOLTAGE (mV)
SENSE CURRENT (A)
DIO Pin Voltage vs Current
2.0 1.8 1.6
DIO VOLTAGE (V) DIO VOLTAGE (V)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 18 20 DIO CURRENT (mA)
1768 G24
-1.4 -1.2 -1.0 - 0.8 - 0.6 - 0.4 - 0.2 0 0 - 2 - 4 - 6 - 8 -10 -12 -14 -16 -18 -20 DIO CURRENT (mA)
1768 G20
VC CLAMP VOLTAGE (V)
UW
1768 G10
PWM Frequency vs Temperature
124 120 116 112 CT = 0.22F VPWM = 2.5V
0.250 0.225 0.200 0.175 0.150 0.125 0.100 0.75 0.50 0.25
FAULT Pin Saturation Voltage vs Temperature
IDIO1 = 0A IDIO2 = 0A IFAULT = 1mA -25 50 0 25 75 TEMPERATURE (C) 100 125
0 -50
1768 G11
1768 G12
Sense Pin Bias Current vs Temperature
50 45 40 VSENSE = 0V
Maximum Gate Voltage vs Temperature
15.00 14.50 14.00 13.50 13.00 12.50 12.00 11.50 11.00 10.50 10.00 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125 VIN = 12V VIN = 24V IGATE = -10mA
1768 G14
1768 G15
DIO Pin Voltage vs Current
- 2.0 -1.8 -1.6 3.75 3.74 3.73 3.72 3.71 3.70 3.69 3.68 3.67 3.66 3.65
VC Clamp Voltage vs Current
0
50 100 150 200 250 300 350 400 450 500 VC CURRENT (A)
1768 G25
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LT1768 TYPICAL PERFOR A CE CHARACTERISTICS
VC Clamp Voltage vs Temperature
3.90
1.00
VC SWITCH THRESHOLD VOLTAGE (V)
3.85 3.80 3.75
VC CLAMP(V)
IVC = 500A
0.85 0.80 0.75 0.70 0.65 0.60 0.55 0.50 -50
PWM INPUT CURRENT (A)
3.70 3.65 3.60 3.55 3.50 3.45 3.40 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125
PWM Pin Input Current vs Temperature
1.40
BULB FAULT CURRENT THRESHOLD (A)
1.30
PWM INPUT CURRENT (A)
VPWM = 2.5V
SENSE THRESHOLD (mV)
1.20 1.10 1.00 0.90 0.80 0.70 0.60 0.50 0.40 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125
IDIO1/2 to IRMAX Ratio vs RMAX Current
110 108
IDI01/2 TO IRMAX RATIO (A/A)
VPROG = 4.5V VVC = 2.5V
IDI01/2 TO IRMAX RATIO (A/A)
104 102 100 98 96 94 92 90 0 -60 -120 -180 IRMAX (A) -240 -300
1768 G33
54 52 50 48 46 44 42 40 0 -60 -120 -180 IRMAX (A) -240 -300
1768 G34
IDI01/2 TO IRMIN RATIO (A/A)
106
6
UW
1768 G26 1768 G29
VC Switching Threshold vs Temperature
25
PWM Pin Input Current vs Voltage
0.95 0.90
20
15
10
5
0
-25
50 0 25 75 TEMPERATURE (C)
100
125
0
1
3 2 PWM VOLTAGE (V)
4
5
1768 G28
1768 G27
Lamp Fault Current Threshold vs Temperature
200 180 160 140 120 100 80 60 40 20 0 -50 -25 50 0 25 75 TEMPERATURE (C) 100 125 120 110 100 90 80 70 60 50 40 30 20
Maximum Sense Threshold vs Gate Drive Duty Cycle
0
10 20 30 40 50 60 70 80 90 100 GATE DUTY CYCLE (%)
1768 G32
1768 G31
IDIO1/2 to IRMAX Ratio vs RMAX Current with a Lamp Fault
60 58 56 VPROG = 4.5V VVC = 2.5V IDI01 OR IDI02 = 0A 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 9.0
IDIO1/2 to IRMIN Ratio vs RMIN Current
VPROG = 0.75V VVC = 2.5V
0
-60
-120
-180 IRMIN (A)
-240
-300
1768 G35
LT1768
PIN FUNCTIONS
PGND (Pin 1): The PGND pin is the high current ground path. High switching current transients and lamp current flow through the PGND pin. DIO1/DIO2 (Pins 3/2): Each DIO pin is the common connection between the cathode and anode of two internal diodes. The remaining terminals of the diodes are connected to PGND. In a typical application, the DIO1/2 pins are connected to the low voltage side of the lamps. Bidirectional lamp current flows into the DIO1/2 pins and their diodes conduct alternately on the half cycles. The diode that conducts on the negative cycle has a percentage of its current diverted into the VC pin. This current nulls against the programming current specified by the PROG and PWM pins. A single capacitor on the VC pin provides both stable loop compensation and an averaging function to the half wave-rectified lamp current. The diode that conducts on the positive cycle is used to detect open lamp conditions. If the current in either of the DIO pins on the positive cycle is less than 125A for a minimum of 1 PWM cycle, then the FAULT pin will be activated and the maximum source current into the VC pin will be reduced by approximately 50%. If the current in both of the DIO pins on the positive cycle is less than 125A, and the VC pin hits its clamp value (indicating either an open lamp or lamp lowside short to ground fault condition) for a minimum of 1 PWM cycle, the gate drive will be latched off. The latch can be cleared by setting the PROG voltage to zero or placing the LT1768 in shutdown mode. SENSE (Pin 4): The SENSE pin is the input to the current sense comparator. The threshold of the comparator is a function of the voltage on the VC pin and the switch duty cycle. The maximum threshold is set at 100mV for duty cycle less than 50% which corresponds to approximately 3.7V on the VC pin. The SENSE pin has a bias current of 25A, which flows out of the pin. VC (Pin 5): The VC pin is the summing junction for the programming current and the half wave rectified lamp current and is also an input to the current sense comparator . A fraction of the voltage on the VC pin is compared to the voltage on the SENSE pin (switch current) for switch turnoff. During normal operation the VC pin sits between 0.7V (zero switch current) and 3.7V (maximum switch current). A single capacitor between VC and AGND provides lamp current averaging and single pole loop compensation. AGND (Pin 6): The AGND pin is the low current analog ground. It is the negative sense terminal for the internal reference and current sense amplifier. Connect critical external components that terminate to ground directly to this pin for best performance. CT (Pin 7): The value of capacitance on the CT pin determines the PWM modulation frequency. The transfer function of capacitance to frequency equals 22Hz/CT(F). The frequency present on the CT pin also determines the maximum time allowed for lamp fault conditions. If the current in either DIO1 or DIO2 is less than 125A for a minimum of 1 PWM period, the FAULT pin is activated and the maximum allowable lamp current is reduced by approximately 50%. If the current in both DIO1 and DIO2 is absent for a minimum of 1 PWM period, and the VC pin is clamped at 3.7V, the FAULT pin is activated and the gate drive of the part is internally latched off. The latch can be cleared by setting the PROG voltage to zero or placing the LT1768 in shutdown mode. PROG (Pin 8): The PROG pin controls the lamp current by converting a DC input voltage range of 0V to 5V to source current into the VC pin. The transfer function from programming voltage to VC current is illustrated in the following table.
PROG (V) VPROG < 0.5 0.5 < VPROG < 1.0 1.0 < VPROG < VPWM VCT > VPROG VCT < VPROG VPROG > 4.0 VC SOURCE CURRENT (A) 0 IRMIN PWM Mode* IRMIN 5 * IRMAX * ( VPWM - 1V)/ 3V 5 * IRMAX
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*PWM Duty Cycle = [1 - (VPWM - VPROG)/(VPWM - 1V)] * 100%
PWM (Pin 9): The PWM pin controls the percentage of the PROG range between 1V and 4V that is to be pulse width modulated. The percentage is defined by [(VPWM-1)/ 3] * 100%. The minimum and maximum percentages are 25% (1.75V) and 100% (4V) respectively. Taking the PWM pin above the 4V maximum will cause significant PWM input current to flow. (See PWM Input Current vs Voltage curve in Typical Performance Characteristics).
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LT1768
PIN FUNCTIONS
RMAX (Pin 10): The RMAX pin outputs a regulated voltage of 1.25V that is to be loaded with an external resistor. The current through the external resistor sets the maximum lamp current. Maximum lamp current in a dual lamp application will be approximately equal to 100 times IRMAX when the voltage on the PROG pin is greater than 4V. The value of RRMAX must be greater than 5K and less than [RRMIN * 2.5 * (VPWM-1/3)] for proper PWM operation. RMIN (Pin 11): The RMIN pin outputs a regulated voltage of 1.26V that is to be loaded with an external resistor. The current through the external resistor sets the minimum lamp current. Minimum lamp current in a dual lamp application will be approximately 10 times the value of IRMIN when the voltage on the PROG pin is between 0.5V and 1V. To set the minimum current to zero (IRMIN = 0A) for maximum dimming range, connect the RMIN pin to the VREG pin. The value of RRMIN (RRMIN = when RMIN is connected to VREG) must be greater than the value of RRMAX/[0.4 * (VPWM-1)/3] for proper PWM operation. SHDN (Pin 12): The SHDN pin controls the operation of the LT1768. Pulling the SHDN pin above 1.26V or leaving the pin open will result in normal operation of the LT1768. Pulling the SHDN pin below 1V causes a complete shutdown of the LT1768 which results in a typical quiescent current of 65A. The SHDN pin has an internal 7A pull-up source to VIN and 200mV of voltage hysteresis. FAULT (Pin 13): The FAULT pin is an open collector output with a sink capability of 1mA that is activated when lamp current falls below 125A in either DIO1 or DIO2 for at least 1 full PWM cycle. VREF (Pin 14): The VREF pin is a regulated 5V output that is derived from the VIN pin. The regulated voltage provides up to 10mA of current to power external circuitry. During undervoltage lockout, shutdown mode or thermal shutdown, drive to the VREF pin will be disabled. VIN (Pin 15): The VIN pin is the voltage supply pin for the LT1768. For normal operation, the VIN pin must be above an undervoltage lockout of 7.9V and below a maximum of 24V. GATE (Pin 16): The GATE pin is the output of a NPN high current output stage used to drive the gate of an external MOSFET. It has a dynamic source and sink capability of 1.5A. During normal operation, the GATE pin is driven high at the beginning of each oscillator period and then low when the appropriate current in the switch is reached. The GATE pin has a minimum on time of 125ns and a maximum duty cycle of 93% at a frequency of 350kHz. For input voltages less than 13V the gate will be driven to within 2V of VIN. For input voltages greater than 13V the gate pin high level will be clamped at a typical voltage of 12.5V.
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LT1768
BLOCK DIAGRA
VIN 15 SHDN 12 VREF UNDERVOLTAGE LOCKOUT THERMAL SHUTDOWN
VREF 14
RMIN 11 RMAX 10
1.26V
IRMIN S IRMAX 0 1V 4V MODE CONTROL IVC VCCLAMP FAULT 4 SENSE Q R
1.25V
PROG 8
PWM 9
VPWM 1V
CT 7
PWM PERIOD
APPLICATIONS INFORMATION
INTRODUCTION The current trend in desktop monitor design is to migrate the LCD (liquid crystal display) technology used in laptops and instruments to the popular desktop display sizes. As LCD size increases uniform backlighting requires multiple high power lamps. In addition, the lamps must have a dimming range and lifetime expectancy comparable to previous generations of desktop displays. Cold cathode fluorescent lamps (CCFLs) provide the highest available efficiency for backlighting LCD displays. The CCFL requires a high voltage supply for operation. Typically, over 1000 volts is required to initiate CCFL operation, with sustaining voltages from 200V to 800V. A CCFL can operate from DC, but migration effects damage the CCFL and shorten its lifetime. To achieve maximum life CCFL drive should be sinusoidal, contain zero DC component, and not exceed the CCFL manufacturers minimum and maximum operating current ratings. Low crest factor sinusoidal CCFL drive also maximizes current to light conversion, reduces display flicker, and minimizes EMI and RF emissions. The LT1768 high power CCFL controller, with its Multimode Dimming, provides the necessary lamp drive to enable a wide dimming range while maintaining lamp lifetime in multiple lamp CCFL applications. BASIC OPERATION Referring to the circuit in Figure 1, CCFL current is controlled by a DC voltage on the PROG pin of the LT1768. The DC voltage on the PROG pin feeds the LT1768's Multimode Dimming block and is converted to source current into the VC pin. As the VC pin voltage rises, the LT1768's GATE pin is pulse width modulated at 350kHz. The GATE pulse width is determined on a cycle by cycle basis by the voltage on the SENSE pin (L1's current multiplied by SENSE resistor R5) exceeding a predetermined voltage set by the VC pin.
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OSC VIN GATE 16 GATE SW BLANK SLOPE MULTI-MODE DIMMING BLOCK (IDIO1 + IDIO2) GAIN IVC 13 FAULT IDIO1 < 125A 1 PGND IDIO2 < 125A
1768 BD
5 VC
6 AGND
3 DI01
2 DIO2
Figure 2. LT1768 Block Diagram
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LT1768
APPLICATIONS INFORMATION
The current mode pulse width modulation produces an average current in inductor L1 proportional to the VC voltage. Inductor L1 then acts as a switched mode current source for a current driven Royer class converter with efficiencies as high as 90%. T1, C4 and Q1 comprise the Royer class converter which provides the CCFLs with a zero DC, 60kHz sinusoidal waveform whose amplitude is based on the average current in L1. Sinusoidal current from both CCFLs is then returned to the LT1768 through the DIO1/2 pins. A fraction of the CCFL current from the negative half of its sine wave pulls against the internal current source at the VC pin closing the loop. A single capacitor on the VC pin provides loop compensation and CCFL current averaging, which results in constant CCFL current. Varying the value of the internal current source via the Multimode Dimming block varies the CCFL current and resultant CCFL light intensity. Multimode Dimming Previous backlighting solutions have used a traditional error amplifier in the control loop to regulate lamp current. The approach converted AC current into a DC voltage for the input of the error amplifier. This approach used several time constants in order to provide stable loop compensation. This compensation scheme meant that the loop had to be fairly slow and that the output overshoot with startup or load conditions had to be carefully evaluated in terms of transformer stress and breakdown voltage requirements. In addition, intensity control schemes were limited to linear or PWM control. Linear intensity control schemes provide the highest efficiency backlight circuits but either limit dimming range, or violate lamp minimum or maximum CCFL current specifications to achieve wide dimming ratios. PWM control schemes offer wide dimming range but produce waveforms that may degrade CCFL life, and waste power at higher CCFL currents. The LT1768's Multimode Dimming eliminates the error amplifier concept entirely and combines the best of both control schemes to extend CCFL life while providing the widest possible dimming range. The error amplifier is eliminated by summing the current out of the Multimode Dimming block with a fraction of feedback lamp current to form the control loop. This topology reduces the number of time constants in the control loop by combining the error signal conversion scheme and frequency compensation into a single capacitor (VC pin). The control loop thus exhibits the response of a single pole system, allows for faster loop transient response and minimizes overshoot under start-up or overload conditions. Referring to Figure 2, the source current into the VC pin from the Multimode Dimming block (and resultant CCFL current) has five distinct modes of operation. Which mode is in use is determined by the voltages on the PROG and PWM pins, and the currents that flow out of the RMAX and RMIN pins. Off Mode (VPROG < 0.5V), sets the VC source current to zero, actively pulls VC to ground, and inhibits the GATE pin from switching which results in zero lamp current. Minimum current mode (0.5V < VPROG < 1V) sets the VC source current equal to the current out of the 1.26V referenced RMIN pin. The minimum VC source current determines the dimming range of the display. Setting RRMIN to produce the manufacturer's minimum specified CCFL current guarantees the maximum CCFL lifetime for all PROG voltages, but limits the dimming range. Setting RRMIN to produce currents less than the manufacturer's minimum specified CCFL current increases dimming range, but places restrictions on the PROG voltage for normal operation in order to maximize lifetime. To achieve the maximum dimming ratio possible, IRMIN should be set to zero by connecting the RMIN pin to the VREF pin. For example, the circuit in Figure 1 produces a dimming ratio of 100:1 at 1mA of lamp current, but sets the minimum CCFL current to zero (RMIN is connected to VREF). In this case, the PROG voltage must be kept above 1.12V to limit the CCFL current to 1mA (1mA is only a typical minimum lamp current used for illustration, consult lamp specifications for actual minimum allowable value) during normal operation in order to meet CCFL specifications to maximize lifetime. It should be noted that taking the PROG voltage in Figure 1 down to 1V (0mA CCFL current) enables dimming ratios greater than 500:1, but violates minimum CCFL current specifications in most lamps and is not recommended. Alternatively, disconnecting RMIN from VREF and adding a 10k resistor from RMIN to AGND in Figure 1 sets the minimum CCFL current
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LT1768
APPLICATIONS INFORMATION
per lamp to 1mA for all PROG voltages but limits the dimming ratio to 6:1. Trace B in Figures 3a and 3b shows Figure 1's CCFL current waveform operating at 1mA in PWM mode. Maximum current mode (VPROG > 4V) sets the VC source current to five times the current out of the 1.25V referenced RMAX pin. Setting RRMAX to produce CCFL current equal to the manufacturer's maximum rating in this mode insures no degradation in the specified lamp lifetime. For example, setting R4 in the circuit in Figure 1 to 16.2k sets the maximum CCFL current to 9mA (9mA is only a typical maximum lamp current used for illustration, consult lamp specifications for the actual value). Trace A in Figure 3a and 3b shows Figure 1's CCFL current waveform operating at 9mA in maximum current mode.
TRACE A VPROG = 4.5V ILAMP = 9mARMS
TRACE B VPROG = 1.125V ILAMP = 1mARMS 1ms/DIV
Figure 3a. CCFL Current for Circuit in Figure 1
TRACE A VPROG = 4.5V ILAMP = 9mARMS
TRACE B VPROG = 1.125V ILAMP = 1mARMS 100s/DIV
Figure 3b. CCFL Current for Circuit in Figure 1
In linear mode (VPWM < VPROG < 4V), VC source current is controlled linearly with the voltage on the PROG pin. The equation for the VC source current in linear mode is IVC = (VPROG - 1V)/3V (IRMAX * 5). For the best current to light conversion and highest efficiency, VPWM should be set to make the LT1768 normally operate in the linear
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mode. For example, in the circuit in Figure 1, linear mode runs from VPROG = 3V to VPROG = 4V with lamp current equal to (3mA)(VPROG-1V)/1V. In PWM Mode (1V < VPROG < VPWM), the VC source current is modulated between the value set by minimum current mode and the value for IVC in linear mode with VPROG = VPWM. The PWM frequency is equal to 22Hz/CT(F) with its duty cycle set by the voltages on the PROG and PWM pins and follows the equation: DC = [1 - (VPWM - VPROG)/(VPWM - 1V)] * 100% The LT1768's PWM mode enables wide dimming ratios while reducing the high crest factor found in PWM only dimming solutions. In the example of Figure 1, PWM mode runs from VPROG = 1V to VPROG = 3V with CCFL current modulated between 0mA and 6mA. The PWM modulation frequency is set to 220Hz by capacitor C3. When combined, these five modes of operation allow creation of a DC controlled CCFL current profile that can be tailored to each particular display. With linear mode CCFL current control over the most widely used current range, and PWM mode at the low end, the LT1768 enables wide dimming ratios while maximizing CCFL lifetimes. Lamp Feedback Current In a typical application, the DIO1/2 pins are connected to the low voltage side of the lamps. Each DIO pin is the common connection between the cathode and anode of two internal diodes (see Block Diagram). The remaining terminals of the diodes are connected to PGND. Bidirectional lamp current flows into the DIO1/2 pins and their diodes conduct alternately on the half cycles. The diode that conducts on the negative cycle has a percentage of its current diverted into the VC pin. This current nulls against the VC source current specified by the Multimode Dimming section. A single capacitor on the VC pin provides both stable loop compensation and an averaging function to the halfwave-rectified lamp current. Therefore, current into the VC pin from the lamp current programming section relates to average lamp current. The overall gain from the resistor current to average lamp current is equal to the gain from the Multimode Dimming block divided by the gain from the DIO pin to the VC pin,
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LT1768
APPLICATIONS INFORMATION
and is dependant on the operating mode. For dual lamp displays, the transfer function for minimum current mode (IDIO/IRMIN) is equal to 10A/A, and for maximum current mode (IDIO/IRMAX) is equal to 100A/A. The transfer functions discussed above are between RMAX and RMIN current and average lamp current not RMS lamp current. Due to the differences between the average and RMS functions, the actual overall transfer function between actual lamp current and RMIN/RMAX current must be empirically determined, and is dependant on the particular lamp/display housing combination used. For example, in the circuit of Figure 1 setting RRMIN to 10k and RRMAX to 16.8, sets the minimum and maximum RMS lamp currents for the example display to 1mA and 9mA per lamp respectively. Figure 4 shows the lamp current vs programming voltage for the circuit in Figure 1.
MIN CURRENT 9mA 6mA ICCFL (mA) LINEAR MAX CURRENT
PWM (FREQ = 220Hz) 0% 100%
OFF 0mA 0.5 1.0 3V (VPWM) 4.0 VPROG(V) 5.0
1768 F04
Figure 4. Lamp Current vs PROG Voltage for the Circuit in Figure 1
Choosing RRMAX and RRMIN and VPWM The value for RRMAX should be determined by setting VPROG to 4.5V then adjusting RRMAX to produce the maximum allowable current specified by the lamp manufacturer. The voltage for the PWM pin should then be set so that the LT1768 normally operates in linear mode. A typical value for VPWM is approximately 2.5V, which limits the PWM region to 50% of the VPROG input voltage range. The value for RRMIN should be chosen to either produce the minimum manufacturer specified lamp current or enable a wide dimming range. If a minimum specified current is desired, the VPROG should be set to 0.75V and
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RRMIN adjusted to produce the specified current. If a wide dimming range is desired, VPROG should be set to 0.75V and RRMIN adjusted to produce the required dimming ratio. Care must be taken when adjusting RRMIN to produce extreme dimming ratios. The minimum lamp current set by RRMIN must be able to fully illuminate the lamp or thermometering (uneven illumination) will occur. If the desired dimming ratio can't be achieved by adjusting RRMIN, the minimum lamp current can be set to zero by connecting the RMIN pin to the VREF pin. If the minimum current is set to less than the open lamp threshold current (approximately 125A), the FAULT pin will be activated for PROG voltages between 0.5V and 1V. The values chosen for RRMAX and RRMIN are extremely critical in determining the lifetime of the display. It is imperative that proper measurement techniques, such as those cited in the references, be used when determining RRMAX and RRMIN values. Lamp Fault Modes and Single Lamp Operation The DIO pin diodes that conduct on the positive cycle are used to detect open lamp fault conditions. If the current in either of the DIO pins on the positive half cycle is less than 125A due to either an open lamp or lamp lowside short to ground, for a minimum of 1 PWM cycle, then the FAULT pin will be activated and the lamp programming current into the VC pin in high level PWM mode, linear mode, and maximum current mode, will be reduced by approximately 50%. Halving the VC source current will cut the total lamp current to approximately one half of its programmed value. This function insures that the maximum lamp current level set by RRMAX will not be exceeded even under fault conditions. If the current in both of the DIO pins on the positive cycle is less than 125A, and the VC pin hits its clamp value (indicating an open lamp or lamp lowside short to ground fault condition) for a minimum of 1 PWM cycle, the gate drive will be latched off. The latch can be cleared by setting the PROG voltage to zero or placing the LT1768 in shutdown mode. Since open lamp fault conditions produce high voltage AC waveforms, it is imperative that proper layout spacings between the high voltage and DIO lines be observed. Coupling capacitance as low as 0.5pF between the high
LT1768
APPLICATIONS INFORMATION
voltage and DIO lines can cause enough current flow to fool the open lamp detection. In situations where coupling can't be avoided, resistors can be added from the DIO pins to ground to increase the open lamp threshold. When resistors from the DIO pins to ground are added, the values for RRMAX and RRMIN may need to be increased from their nominal values to compensate for the additional current. For single lamp operation, the lowside of the lamp should be connected to both DIO pins, and the values of RRMAX and RRMIN increased to two times the values that would be used in a dual lamp configuration. In single lamp mode all fault detection will operate as in the dual lamp configuration, but the open lamp threshold will double. If the increase in the open lamp threshold is not acceptable, a positive offset current can be added to reduce the open lamp threshold by placing a resistor between the REF and DIO pins (a 33k resistor will reduce the open lamp threshold by approximately 100A ((VREF - VDIO+)/33k). When an offset current is added, the values for RRMAX and RRMIN may need to be increased from their nominal values to compensate for the offset current. VC Compensation As previously mentioned a single capacitor on the VC pin combines the error signal conversion, lamp current averaging and frequency compensation. Careful consideration should be given to the value of capacitance used. A large value (1F) will give excellent stability at high lamp currents but will result in degraded line regulation in PWM mode. On the other hand , a small value (10nF) will give excellent PWM response but might result in overshoot and poor load regulation. The value chosen will depend on the maximum load current and dimming range. After these parameters are decided upon, the value of the VC capacitor should be increased until the line regulation becomes unacceptable. A typical value for the VC capacitor is 0.033F. For further information on compensation please refer to the references or consult the factory. Current Sense Comparator The LT1768 is a current mode PWM controller. Under normal operating conditions the GATE is driven high at the start of every oscillator cycle. The GATE is driven back low when the current reaches a threshold level proportional to the voltage on the VC pin. The GATE then remains low until the start of the next oscillator cycle. The peak current is thus proportional to the VC voltage and controlled on a cycle by cycle basis. The peak switch current is normally sensed by placing a sense resistor in the source lead of the output MOSFET. This resistor converts the switch current to a voltage that can be compared to a fraction of the VC voltage [(VVC - VDIODE)/30] . For normal conditions and a GATE duty cycle below 50%, the switch current limit will correspond to IPK = 0.1/RSENSE. For GATE duty cycles above 50% the switch current limit will be reduced to approximately 90mV at 80% duty cycle to avoid subharmonic oscillations associated with current mode controllers. When the lamp current is programmed to PWM mode, the VC pin will slew between voltages that represent the minimum and maximum PWM lamp currents. The slew time affects the line regulation at low duty cycle, and should be kept low by making the sense resistor as small as possible. The lowest value of sense resistor is determined by switching transients and other noise due to layout configurations. A good rule of thumb is to set the sense resistor so that the voltage on the VC pin equals 2.5V when the PWM current is in maximum mode (VPROG = VPWM). Typical values of the sense resistor run in the 25m to 50m range for large displays, and can be implemented with a copper trace on the PCB. Since the maximum threshold at the SENSE pin is only 100mV, switching transients and other noise can prematurely trip the comparator. The LT1768 has a blanking period of 100ns which prohibits premature switch turn off, but further filtering the sense resistor voltage is recommended. A simple RC filter is adequate for most applications. (Figure 5.)
GATE LT1768 SENSE 2.2nF 0.025m
1768 *F05
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100
Figure 5. Sense Pin Filter
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LT1768
APPLICATIONS INFORMATION
GATE The LT1768 has a single high current totem pole output stage. This output stage is capable of driving up to 1.5A of output current. Cross-conduction current spikes in the totem pole output have been eliminated. The GATE pin is intended to drive an N-channel MOSFET switch. Rise and fall times are typically 50ns with a 3000pF load. A clamp is built into the device to prevent the GATE pin from rising above 13V in order to protect the gate of the MOSFET switch. The GATE pin connects directly to the emitter of the upper NPN drive transistor and the collector of the lower NPN drive transistor in the totem pole. The collector of the lower transistor, which is N-type silicon, forms a P-N junction with the substrate of the device. This junction is reversed biased during normal operation. In some applications the parasitic LC of the external MOSFET gate can ring and pull the GATE pin below ground. If the GATE pin is pulled negative by more than a diode drop the parasitic diode formed by the collector of the GATE NPN and the substrate will turn on. This can cause erratic operation of the device. In these cases a Schottky clamp diode is recommended from the GATE pin to ground. (Figure 6.)
BAT 85
LT1768 PGND GATE
1768 * G06
Figure 6. Schottky Gate Clamp
Reference The internal reference of the LT1768 is a trimmed bandgap reference. The reference is used to power the majority of the LT1768 internal circuitry. The reference is inactive if the LT1768 is in undervoltage lockout, shutdown mode, or thermal shutdown. The undervoltage lockout is active when VIN is below 7.9V and the LT1768 is in shutdown mode when the voltage on the SHDN pin is pulled below 1V. The SHDN pin has 200mV of hysteresis and a 7A pull-
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up current source. The LT1768 thermal shutdown temperature is set at 160C. A buffered version of the internal 5V is present at the VREF pin and is capable of supplying up to 10mA of current. Note that using any substantial amount of current from the VREF pin will increase power dissipation in the device, which will reduce the useful operating ambient temperature range. Supply and Input Voltage Sequencing For most applications, where the SHDN pin is left floating, and the voltages on the PWM and PROG pins are derived from the VREF pin, the LT1768 will power-up and powerdown correctly when the voltage to the VIN pin is applied and removed. In applications where the voltage inputs for the VIN pin, SHDN pin, PWM pin, and the PROG pin originate from different sources (power supply, microprocessors etc.), care must be taken during power up/down sequences. For proper operation during the power-up sequence, the voltage on the following pins must be taken from zero to their appropriate values in the following order; VIN pin, SHDN pin, PWM pin and PROG pin. For proper operation during the power-down sequence, the order must be reversed. For example, in the circuit of Figure 1 where the SHDN pin is left floating, and the PWM pin voltage is derived from a resistor divider to the VREF pin, the proper power-up sequence would be to take the VIN pin from zero to its value then apply either a voltage or PWM signal to the PROG pin. The power-down sequence for the circuit in Figure 1 would be to take the PROG pin voltage to zero, then take the VIN pin voltage to zero.If the PROG voltage in the circuit of Figure 1 is present before the VIN supply voltage, proper power supply sequecing can be achieved by implementing the circuit shown in Figure 7.
VIN LT1768 0 TO 5V OR 1kHz PWM 49.9k PROG VN2222LL 10k 10F
1768 F07
Figure 7. Circuit Insures Proper Supply Sequencing When Dimming Voltage Exists Before Main Power Supply
LT1768
APPLICATIONS INFORMATION
Supply Bypass and Layout Considerations Proper supply bypassing and layout techniques must be used to insure proper regulation, avoid display flicker, and insure long term reliability. Figure 8 shows the application's critical high current paths in thick lines. Ideally, all components in the high current path should be placed as close as possible and connected with short thick traces. The most critical consideration is that T1's center tap, the Schottky diode D1, LT1768's VIN pin, and a low ESR capacitor (C1) be connected directly
T1
VIN C2 *OPTIONAL
L1 D1
LT1768 VIN C1 GATE SENSE PGND BOLD LINES INDICATE HIGH CURRENT PATHS
1768 F08
Figure 8
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together with minimum trace between them. If space constraints prohibit the transformer T1 placement next to C1, local bypassing (C2) for the center tap of transformer T1 should be used. Special attention is also required for the layout of the high voltage section to avoid any unpleasant surprises. Please refer to the references for an extensive discussion on high voltage layout techniques. Applications Support Linear Technology invests an enormous amount of time, resources, and technical expertise in understanding, designing and evaluating backlight solutions for systems designers. The design of an efficient and compact backlight system is a study of compromise in a transduced electronic system. Every aspect of the design is interrelated and any design change requires complete re-evaluation for all other critical design parameters. Linear Technology has engineered one of the most complete test and evaluation setups for backlight designs and understands the issues and trade-offs in achieving a compact, efficient and economical customer solution. Linear Technology welcomes the opportunity to discuss, design, evaluate, and optimize any backlight system with a customer. For further information on backlight designs, consult the references below. References 1. Williams, Jim. November 1995. A Fourth Generation of LCD Backlight Technology. Linear Technology Corporation, Application Note 65.
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LT1768
TYPICAL APPLICATIONS
DC Intensity Control
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VREF R1 100k POT PROG LT1768 AGND
1768 TA04
PWM Intensity Control
0 - >5V 1kHz PWM
R1 49.9k C1 10F
VREF PROG LT1768 AGND
1768 TA05
PWM Intensity Control From 3.3V or 5V Logic
VREF R1 10k PROG R1 49.9k RID C1 10F LT1768 AGND
0 - >3.3V OR 0 - >5V 1kHz PWM
Q1 VN2222LL
1768 TA06
LT1768
TYPICAL APPLICATIONS
2-Wire Serial interface Intensity Control
SCL VCC VREF PROG LT1768 AGND
1768 TA08
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VOUT SDA LTC1663 GND
Pushbutton Intensity Control
R1 50k
S1 CLK1 S2 SHDN VREF PROG LT1768 AGND
VCC CLK2 LTC1426 AGND VREF PWM2 PWM1
R1 49.9k C1 10F
1768 TA07
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LT1768
TYPICAL APPLICATIONS
X2 LAMP LAMP LAMP CTX110607 CTX110607 T2 T3 T1 C15, 22pF C14, 22pF X3 X4 R11 1k D4 BAT54
C13, 22pF
R10 1k
CTX110607 T4
CTX110607
D3 BAT54
VIN = 12V C1 33F C8, 0.22F C9, 0.22F R7 499 R6 499 Q1A ZDT1048 Q1B ZDT1048 5V FAULT SHUTDOWN D2 MBRS130LT3 L2 22H R5 125k C5 0.1F L1 22H
C10, 0.22F
C11, 0.22F
1
PGND
GATE
16
2
DI02
15
VIN
3
DI01
VREF
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4
C2 0.047F
13 SENSE FAULT LT1768 12 5 VC SHDN
6
AGND
RMIN
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7
C3 0.1F R2 30.1k R3 69.8k C7 2200pF R8 100
CT
RMAX
R4 10 11.3k
8
PROG
PWM
9
PROG 0V TO 5V OR 1kHz PWM C6 1F
Q2 Si3456DV R9 0.0125
1768 TA10
R1 49.9k
C4 10F
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24 Watt Four Lamp CCFL Supply
X1 LAMP C12, 22pF
LT1768
PACKAGE DESCRIPTIO U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 - 0.244 (5.817 - 6.198) 0.150 - 0.157** (3.810 - 3.988) 1 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727) 23 4 56 7 8 0.004 - 0.0098 (0.102 - 0.249) 0.008 - 0.012 (0.203 - 0.305) 0.0250 (0.635) BSC
GN16 (SSOP) 1098
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1768
TYPICAL APPLICATION
4 Watt Single Lamp CCFL Supply
C9 33pF X1 LAMP T1 CTX110607 VIN = 9V TO 24V C1 33F 1 2 3 4 5 C2 0.047F 6 7 C3 0.22F PROG 0V TO 5V OR 1kHz PWM 8 PGND DI02 DI01 GATE VIN VREF 14 13 FAULT SHUTDOWN 5V C5 0.1F R5 124k D2 MBRS130LT3 16 15 R7 499 C7 0.33F
R1 49.9k
C4 10F
RELATED PARTS
PART NUMBER LT1170 LT1182/LT1183 LT1184 LT1186 LT1372 LT1373 LT1786F DESCRIPTION Current Mode Switching Regulator CCFL/LCD Contrast Switching Regulators CCFL Current Mode Switching Regulator CCFL Current Mode Switching Regulator 500kHz, 1.5A Switching Regulator 250kHz, 1.5A Switching Regulator SMBus Controlled CCFL Switching Regulator COMMENTS 5.0A, 100kHz 3V VIN 30V, CCFL Switch: 1.25A, LCD Switch: 625mA, Open Lamp Protection, Positive or Negative Contrast 1.25A, 200kHz 1.25A, 100kHz, SMBus Interface Small 4.7H Inductor, Only 0.5 Square Inch of PCB 1mA IQ at 250kHz, Regulates Positive or Negative Outputs Precision 100A Full Scale Current DAC
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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CT
Q1A ZDT1048
Q1B ZDT1048
SENSE FAULT LT1768 12 VC SHDN AGND RMIN RMAX PWM 11
R4 10 31.6k 9 R2 39.2k R3 61.9k
L1 33H
PROG
Q2 Si3456DV R2 100 R6 0.05
1768 TA09
C6 1F
C8 1000pF
sn1768 1768fs LT/TP 0901 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2000

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